Technologies for preserving error correction capability in compute-near-memory operations

ABSTRACT

Technologies for preserving error correction capability in compute-near-memory operations in a memory include memory media and a media access circuitry coupled with the memory media. The media access circuitry is to detect an error code adjustment state indicative of a failure in the initiated error correction. The media access circuitry is to adjust a voltage to the memory media to eliminate the error code correction adjustment state. Once eliminated, the media access circuitry is to perform the error correction on the read data.

BACKGROUND

Ensuring the reliability of data is a significant challenge for memory and storage devices. A typical approach is to perform, with a memory controller, an error correction code (ECC) process, which involves encoding (e.g., during a writing process) a data set with redundant bits and decoding (e.g., during a reading process) the data set while using the redundant bits to detect and correct errors in the data set. The memory controller may then provide the error-corrected data to a processor or other component (e.g., an accelerator device) to perform operations on the error-corrected data. To mitigate the overhead caused by the redundant bits, the size of each data set to be protected from corruption tends to be relatively large, such as two kilobits or four kilobits. However, the above scheme presents inefficiencies for architectures in which computations may be performed in the memory on the data (e.g., on a memory die, rather than by a processor or other component of a compute device). More specifically, sending data (e.g., through a bus) from the memory media on which the data resides to the memory controller to perform an error correction process and then sending the error-corrected data back from the memory controller through the bus consumes energy and time and may diminish any efficiencies that would otherwise be obtained by performing computations in the memory. Further, based on an amount and frequency of read operations occurring within the memory, the amount of error bits to be corrected may increase. In cases where the strength of an error code correction is limited (e.g., for portability), the error code correction can be ineffective if the amount of error bits is too high.

BRIEF DESCRIPTION OF THE DRAWINGS

The concepts described herein are illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.

FIG. 1 is a simplified diagram of at least one embodiment of a compute device for preserving error code correction capability in a memory or storage media for in-memory compute operations;

FIG. 2 is a simplified diagram of at least one embodiment of a memory media included in the compute device of FIG. 1;

FIG. 3 is a simplified diagram of at least one embodiment of partitions of the memory media and components of a media access circuitry of a memory included in the compute device of FIG. 1;

FIG. 4 is a simplified diagram of at least one embodiment of a tensor operation that may be performed in the memory of the compute device of FIG. 1; and

FIGS. 5 and 6 are simplified diagrams of at least one embodiment of a method for preserving error code correction capability in the memory of the compute device of FIG. 1.

DETAILED DESCRIPTION OF THE DRAWINGS

While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.

References in the specification to “one embodiment,” “an embodiment,” “an illustrative embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).

The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device).

In the drawings, some structural or method features may be shown in specific arrangements and/or orderings. However, it should be appreciated that such specific arrangements and/or orderings may not be required. Rather, in some embodiments, such features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments and, in some embodiments, may not be included or may be combined with other features.

Referring now to FIG. 1, a compute device 100 for preserving error code correction capability in a memory or storage media for in-memory compute operations includes a processor 102, memory 104, an input/output (I/O) subsystem 112, a data storage device 114, and communication circuitry 122. Of course, in other embodiments, the compute device 100 may include other or additional components, such as those commonly found in a computer (e.g., a display, peripheral devices, etc.). Additionally, in some embodiments, one or more of the illustrative components may be incorporated in, or otherwise form a portion of, another component. The compute device 100, and in particular, the memory 104 of the compute device 100 provides multiple levels of error correction, with one level performed within media access circuitry 108 (e.g., by a compute-class ECC logic unit 134) and another level provided by a memory controller 106 (e.g., by a storage-class ECC logic unit 150). As further described herein, the media access circuitry 108, in the illustrative embodiment, is local to (e.g., on the same die, in the same package, etc.) a memory media 110 and may perform compute operations on data from the memory media 110, thereby eliminating the need for data to be sent (e.g., through a bus) to the processor 102 or another component of the compute device 100 for in-memory computations.

Because the media access circuitry 108 is located on the same die as the memory media 110 and executes compute operations on data stored in the memory media 110, it is desirable to maintain error correction operations within the die rather than require the media access circuitry 108 to send data outside the memory, such as to the memory controller 106, to perform error correction. As further described herein, to facilitate the performance of compute operations in the media access circuitry 108, the compute-class ECC logic unit 134 in the media access circuitry 108 produces an error-corrected version of data read from the memory media 110. Doing so ensures that the error correction is performed in-die and eliminates the need for sending the data, in such in-memory operations, to the memory controller 106 for error correction. Further, in producing error-corrected data, the media access circuitry 108 may make the error corrected read data accessible for other processes (e.g., other in-memory compute operations). Doing so increases the efficiency of in-memory compute operations in the memory media 110.

The compute-class ECC logic unit 134 may be embodied as any device or circuitry (e.g., reconfigurable circuitry, an application specific integrated circuit (ASIC), etc.) configured to determine whether data read from the memory media 110 contains errors and to correct any errors with error correction algorithm(s), such as Reed-Solomon codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, or Low Density Parity Check (LDPC) codes. Similarly, the storage-class ECC logic unit 150 may be embodied as any device or circuitry (e.g., reconfigurable circuitry, an application specific integrated circuit (ASIC), etc.) configured to determine whether data read from the memory media 110 (e.g., sent by the media access circuitry 108) contains errors and to correct any errors with error correction algorithm(s), such as Reed-Solomon codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, or Low Density Parity Check (LDPC) codes. In the illustrative embodiment, the compute-class ECC logic unit 134 may be configured to operate on smaller data sets (e.g., 512 bits) than the storage-class ECC logic unit 150, which may operate on data sets of 2 kilobits, 4 kilobits, or other sizes. Similarly, the compute-class ECC logic unit 134 may execute a faster, less compute intensive error correction algorithm (e.g., a BCH algorithm) than an algorithm (e.g., a Reed-Solomon algorithm) executed by the storage-class ECC logic unit 150, as data corrected by the compute-class ECC logic unit 134 typically is retained in the memory for a shorter period of time (e.g., data temporarily written to memory as compute operations are performed in the memory 104), resulting in fewer errors than data corrected by the storage-class ECC logic unit 150.

The memory media 110, in the illustrative embodiment, has a three-dimensional cross point architecture that has data access characteristics that differ from other memory architectures (e.g., dynamic random access memory (DRAM)), such as enabling access to one bit per tile and incurring time delays between reads or writes to the same partition or other partitions. The media access circuitry 108 is configured to make efficient use (e.g., in terms of power usage and speed) of the architecture of the memory media 110, such as by accessing multiple tiles in parallel within a given partition, utilizing scratch pads (e.g., relatively small, low latency memory) to temporarily retain and operate on data read from the memory media 110, and broadcasting data read from one partition to other portions of the memory 104 to enable matrix calculations to be performed in parallel within the memory 104. Additionally, in the illustrative embodiment, instead of sending read or write requests to the memory 104 to access matrix data, the processor 102 may send a higher-level request (e.g., a type of matrix calculation to perform) and provide the locations and dimensions (e.g., in memory) of the matrices to be utilized in the requested operation (e.g., an input matrix, a weight matrix, and an output matrix). Further, rather than sending back the resulting data to the processor 102, the memory 104 may merely send back an acknowledgement (e.g., “Done”), indicating that the requested operation has been completed. As such, many compute operations, such as artificial intelligence operations (e.g., tensor operations involving matrix calculations) can be performed in memory 104, with minimal usage of the bus between the processor 102 and the memory 104. In some embodiments the media access circuitry 108 is included in the same die as the memory media 110. In other embodiments, the media access circuitry 108 is on a separate die but in the same package as the memory media 110. In yet other embodiments, the media access circuitry 108 is in a separate die and separate package but on the same dual in-line memory module (DIMM) or board as the memory media 110.

The processor 102 may be embodied as any device or circuitry (e.g., a multi-core processor(s), a microcontroller, or other processor or processing/controlling circuit) capable of performing operations described herein, such as executing an application (e.g., an artificial intelligence related application that may utilize a neural network or other machine learning structure to learn and make inferences). In some embodiments, the processor 102 may be embodied as, include, or be coupled to an FPGA, an application specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other specialized hardware to facilitate performance of the functions described herein.

The memory 104, which may include a non-volatile memory (e.g., a far memory in a two-level memory scheme), includes the memory media 110 and the media access circuitry 108 (e.g., a device or circuitry, such as integrated circuitry constructed from complementary metal-oxide-semiconductors (CMOS) or other materials) underneath (e.g., at a lower location) and coupled to the memory media 110. The media access circuitry 108 is also connected to the memory controller 106, which may be embodied as any device or circuitry (e.g., a processor, a co-processor, dedicated circuitry, etc.) configured to selectively read from and/or write to the memory media 110 and to perform tensor operations on data (e.g., matrix data) present in the memory media 110 (e.g., in response to requests from the processor 102, which may be executing an artificial intelligence related application that relies on tensor operations to train a neural network and/or to make inferences). Referring briefly to FIG. 2, the memory media 110, in the illustrative embodiment, includes a tile architecture, also referred to herein as a cross point architecture (e.g., an architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance), in which each tile (e.g., memory cell) is addressable by an x parameter and a y parameter (e.g., a column and a row). The memory media 110 includes multiple partitions, each of which includes the tile architecture. The partitions may be stacked as layers 202, 204, 206 to form a three-dimensional cross point architecture (e.g., Intel 3D XPoint™ memory). Unlike typical memory devices, in which only fixed-size multiple-bit data structures (e.g., byte, words, etc.) are addressable, the media access circuitry 108 is configured to read individual bits, or other units of data, from the memory media 110 at the request of the memory controller 106, which may produce the request in response to receiving a corresponding request from the processor 102.

Referring back to FIG. 1, the media access circuitry 108, in the illustrative embodiment, includes a tensor logic unit 130, which may be embodied as any device or circuitry (e.g., CMOS circuitry) configured to offload the performance of tensor operations from other portions of the media access circuitry 108. The tensor logic unit 130, in the illustrative embodiment, includes multiple memory scratch pads 132, each of which may be embodied as any device or circuitry (e.g., static random access memories (SRAMs), register files, etc.) usable to provide relatively fast (e.g., low latency) access to data (e.g., matrix data) that has been read from the memory media 110. In the illustrative embodiment, the scratch pads 132 provide faster read and write access times than the memory media 110 which has comparatively slower access times and a larger capacity. The tensor logic unit 130 additionally includes the compute-class error correction code (ECC) logic unit 134 discussed above. Additionally, in the illustrative embodiment, the tensor logic unit 130 includes multiple compute logic units 136 each of which may be embodied as any device or circuitry (e.g., reconfigurable circuitry, ASICs, etc.) configured to perform compute operations on data read from the memory media 110 (e.g., after the compute-class ECC logic unit 134 has performed an error correction process on the data).

Referring briefly to FIG. 3, in the illustrative embodiment, components of the memory 104 are divided into clusters 310, 320, 330 (e.g., groupings of components). The cluster 310 includes multiple partitions 311 of the memory media 110, a set of scratch pads 312, 314, 316, each similar to the scratch pads 132 of FIG. 1, and a corresponding compute logic unit 318, similar to the compute logic unit 136 of FIG. 1. Similarly, the cluster 320 includes another set of partitions 321 of the memory media 110, a corresponding set of scratch pads 322, 324, 326, and a corresponding compute logic unit 328. The cluster 330 also includes a set of partitions 331 of the memory media 110, a corresponding set of scratch pads 332, 334, 336, and a compute logic unit 338. In the illustrative embodiment, in operation, the compute logic unit 318 reads a subset of data (e.g., one value of an input matrix A from the set of partitions (e.g., partitions 311)) and provides the read data to the compute-class ECC logic unit 134 to perform an error correction process to correct any errors in the data. The compute logic unit 318 may additionally write the data (e.g., after the error correction process has been performed) into the corresponding scratch pad 312 and may broadcast that same subset of the matrix data to the corresponding scratch pads of the other clusters (e.g., to the scratch pads 322, 332). Similarly, the compute logic unit 328 may read, from the corresponding set of partitions 321 another subset of the matrix data (e.g., another value of the input matrix A) into the corresponding scratch pad 322, utilizing the compute-class ECC logic unit 134 to correct any errors, and broadcast that subset of the matrix data to the other scratch pads that are to store data for that matrix (e.g., to the scratch pads 312, 332). The compute logic unit 338 may perform similar operations.

By broadcasting, to the other scratch pads, matrix data that has been read from a corresponding set of partitions of the memory media 110, the media access circuitry 108 reduces the number of times that a given section (e.g., set of partitions) of the memory media 110 must be accessed to obtain the same matrix data (e.g., the read matrix data may be broadcast to multiple scratch pads after being read from the memory media 110 once, rather than reading the same matrix data from the memory media 110 multiple times). Further, by utilizing multiple compute logic units 318, 328, 338 that are each associated with corresponding scratch pads 312, 314, 316, 322, 224, 226, 232, 234, 236, the media access circuitry 108 may perform the portions of a tensor operation (e.g., matrix multiply and accumulate) concurrently (e.g., in parallel). It should be understood that while three clusters 310, 320, 330 are shown in FIG. 3 for simplicity, the actual number of clusters and corresponding partitions, scratch pads, and compute logic units may differ depending on the particular embodiment.

In addition, the illustrative media access circuitry 108 includes a media management logic unit 340 and a state machine 342. In some cases, the memory media 110 may use reference voltages to regulate voltage therein, e.g., as a function of the present usage of data stored in the memory media 110. Relatedly, reference voltages may be used to determine data values at locations in the memory (e.g., if a measured voltage at a location in the memory media is less than a reference voltage, then the value at that location is determined to be zero, otherwise the value is determined to be one). At certain periods of time, the memory media 110 may be subject to a relatively high number of read access operations. Changes in voltage may cause memory resistance drifting, and in turn, an amount of error bits needing correction by error correction techniques may increase. As a result, an error code correction adjustment situation (e.g., a situation in which the compute-class ECC logic unit 134 is unable to correct errors for data that is read from the memory media 110) may occur. Consequently, in-memory compute operations can potentially perform on error-afflicted read data.

To address this, the media access circuitry 108 is configured with a feedback mechanism (e.g., via the media management logic unit 340 and the state machine 342) to adjust reference voltage set by the memory media 110 for read accesses. For instance, the illustrative media management logic unit 340 may be embodied as any device or circuitry to transmit a signal or message to the memory media 110 indicative of a reference voltage value, determined as a function of a present reference voltage. The memory media 110, in turn, may set the reference voltage value to the received reference voltage value such that error bits resulting from read data are correctable by the compute-class ECC logic unit 134. In an embodiment, the state machine 342 may be embodied as any device or circuitry to monitor a state of the components in the memory 104, such as the compute-class ECC logic unit 134 and compute logic unit 136. Further, the state machine 342 may detect changes in state of such components, such as whether the compute-class ECC logic unit 134 is unable to handle error correction in data accessed by the media access circuitry 108 (e.g., due to an amount of error bits in the data being larger than what the compute-class ECC logic unit 134 is capable of correcting due to strength limitations in the compute-class ECC logic unit 134). In such a case, the compute-class ECC logic unit 134 may transmit a signal to the state machine 342 indicating that the compute-class ECC logic unit 134 is in an error code correction adjustment state. Further still, in response to such changes, the state machine 342 may transmit signals to the components to cause the components to perform in a given manner. For example, the state machine 342 may transmit a signal to the media management logic unit 340 to pause a compute operation, e.g., in instances in which the state machine 342 detects that the memory media 110 is in an error code correction adjustment state. The state machine 342 may also transmit a signal to the media management logic 340 to retune the read reference voltage in the memory media 110. Doing so enables the reference voltage to be periodically adjusted such that the amount of error bits in read data is reduced.

Referring briefly to FIG. 4, an example of a matrix multiplication (e.g., matrix multiply and accumulate) operation 400 that may be performed by the memory 104 is shown. As illustrated, matrix data in an input matrix A is multiplied by matrix data in another matrix B (e.g., weight data for a layer of a convolutional neural network) and the resultant data is written to the output matrix C. Each matrix represented in FIG. 4 is temporarily stored as matrix data in the scratch pads 132 of the media access circuitry 108. In some embodiments, the output matrix C may be utilized as an input matrix for a subsequent tensor operation (e.g., as an input matrix for a subsequent layer of a convolutional neural network).

Referring back to FIG. 1, the memory 104 may include non-volatile memory and volatile memory. The non-volatile memory may be embodied as any type of data storage capable of storing data in a persistent manner (even if power is interrupted to the non-volatile memory). For example, the non-volatile memory may be embodied as one or more non-volatile memory devices. The non-volatile memory devices may include one or more memory devices configured in a cross point architecture that enables bit-level addressability (e.g., the ability to read from and/or write to individual bits of data, rather than bytes or other larger units of data), and are illustratively embodied as three-dimensional (3D) cross point memory. In some embodiments, the non-volatile memory may additionally include other types of memory, including any combination of memory devices that use chalcogenide phase change material (e.g., chalcogenide glass), ferroelectric transistor random-access memory (FeTRAM), nanowire-based non-volatile memory, phase change memory (PCM), memory that incorporates memristor technology, Magnetoresistive random-access memory (MRAM) or Spin Transfer Torque (STT)-MRAM. The volatile memory may be embodied as any type of data storage capable of storing data while power is supplied volatile memory. For example, the volatile memory may be embodied as one or more volatile memory devices, and is periodically referred to hereinafter as volatile memory with the understanding that the volatile memory may be embodied as other types of non-persistent data storage in other embodiments. The volatile memory may have an architecture that enables bit-level addressability, similar to the architecture described above.

The processor 102 and the memory 104 are communicatively coupled to other components of the compute device 100 via the I/O subsystem 112, which may be embodied as circuitry and/or components to facilitate input/output operations with the processor 102 and/or the main memory 104 and other components of the compute device 100. For example, the I/O subsystem 112 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In some embodiments, the I/O subsystem 112 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with one or more of the processor 102, the main memory 104, and other components of the compute device 100, in a single chip.

The data storage device 114 may be embodied as any type of device configured for short-term or long-term storage of data such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, or other data storage device. In the illustrative embodiment, the data storage device 114 includes a memory controller 116, similar to the memory controller 106, a storage-class ECC logic unit 160, similar to the storage-class ECC logic unit 150, storage media 120, similar to the memory media 110, and media access circuitry 118, similar to the media access circuitry 108, including a tensor logic unit 140, similar to the tensor logic unit 130, scratch pads 142, similar to the scratch pads 132, a compute-class ECC logic unit 144, similar to the compute-class ECC logic unit 134, and compute logic units 146, similar to the compute logic units 136. As such, in the illustrative embodiment, the data storage device 114 is capable of performing multiple levels of error correction and performing compute operations on data stored in the storage media 120. The data storage device 114 may include a system partition that stores data and firmware code for the data storage device 114 and one or more operating system partitions that store data files and executables for operating systems.

The communication circuitry 122 may be embodied as any communication circuit, device, or collection thereof, capable of enabling communications over a network between the compute device 100 and another device. The communication circuitry 122 may be configured to use any one or more communication technology (e.g., wired or wireless communications) and associated protocols (e.g., Ethernet, Bluetooth®, Wi-Fi®, WiMAX, etc.) to effect such communication.

The illustrative communication circuitry 122 includes a network interface controller (NIC) 124, which may also be referred to as a host fabric interface (HFI). The NIC 124 may be embodied as one or more add-in-boards, daughter cards, network interface cards, controller chips, chipsets, or other devices that may be used by the compute device 100 to connect with another compute device. In some embodiments, the NIC 124 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the NIC 124 may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC 124. In such embodiments, the local processor of the NIC 124 may be capable of performing one or more of the functions of the processor 102. Additionally or alternatively, in such embodiments, the local memory of the NIC 124 may be integrated into one or more components of the compute device 100 at the board level, socket level, chip level, and/or other levels.

Referring now to FIGS. 5 and 6, the compute device 100, in operation, may execute a method 500 for preserving error code correction capability (e.g., of the compute-class ECC logic unit 134). In this example, the method 500 is carried out by the memory 104. However, one of ordinary skill in the art will recognize that the method 500 could be additionally or alternatively performed using the memory of the data storage device 114.

As shown, the method 500 begins in block 502, in which the compute device 100 (e.g., by the media access circuitry 108) reads, from the memory media 110, data specified in a request to perform a compute operation. More particularly, in block 504, the compute device 100 reads, with the media access circuitry 108 that is located on the same die as the memory media 110. The read data may include error code correction (ECC) bits to be used in an ECC operation to ensure that the read data includes no (or minimal) errors. In some cases, the underlying compute operation may correspond to a tensor operation (e.g., a matrix multiplication operation on data stored in the memory media 110) originating from the processor 102 and through the memory controller 106. The request may specify the data in the memory media 110 to be used in the compute operation. In reading the data, the media access circuitry 108 may read the data from a memory media (e.g., the memory media 110) having a cross point architecture (e.g., an architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance). Further, the media access circuitry 108 may read the data from a memory media (e.g., the memory media 110) having a three dimensional cross point architecture (e.g., an architecture in which sets of tiles are stacked as layers, as described with reference to FIG. 2).

In block 506, the compute device 100 performs error correction on the read data using the ECC bits. The error correction may correspond to an error correction algorithm such as a BCH algorithm or a Reed-Solomon error correction algorithm. For instance, in block 508, the media access circuitry 108 may do so via the compute-class ECC logic unit 134. In doing so, the media access circuitry 108 performs, with the compute-class ECC logic unit 134, the error correction in the same die as the memory media 110. Further, in doing so, the compute device 100 performs the error correction with an error correction logic unit that is different from an error correction logic unit in the memory controller (e.g., the storage-class ECC logic unit 150). In performing error correction, the compute device 100 produces error-corrected read data, in which one or more errors in the read data, if any, are corrected.

As stated, in some cases, an ECC operation on the read data may be unsuccessful, e.g., due to error bits in the read data exceeding a threshold count of error bits sometimes caused by reference shift in voltage in the memory media 110. In block 510, the compute device 100 may determine whether the error correction is successful. For instance, the error correction operation may return an error notification indicating that the error correction was unsuccessful.

If the error correction is successful (e.g., the error code correction algorithm was successfully able to produce error-corrected read data), the method 500 proceeds to block 512, in which the compute device 100 determines whether an ECC adjustment state is present, e.g., if a signal has been transmitted to the state machine 342 indicating that such a state is present. If not, then in block 518, the compute device 100 performs the compute operation using the error-corrected read data. The compute device 100 may return the result of the in-memory compute operation to the requesting entity, such as the processor 102. While operations are described as being performed on specific data sizes (e.g., 512 bytes, 2 kilobits, 4 kilobits), it should be understood that in other embodiments, the data sizes may differ.

Referring briefly to FIG. 6, if the error correction is not successful (block 510), then at block 602, the compute device 100 transmits, by the compute-class ECC logic unit 134, a signal to the state machine 342. The signal may be indicative of an ECC adjustment state in which the compute-class ECC logic unit 134 is presently unable to successfully perform error correction (e.g., due to the reference voltage in the memory media 110). Doing so triggers the media management logic unit 340 eliminate the ECC adjustment state. More particularly, in block 604, the compute device 100, by the media management logic unit 340, adjusts a voltage to the memory media 110 to eliminate the error code correction adjustment state. For instance, in block 606, the media management logic unit 340 pauses the pending compute operation. To do so, the media management logic unit 340 may transmit, in response to the signal, an instruction signal to the compute logic unit 136 directing the compute logic unit 136 to temporarily pause the compute operation.

Further, in block 608, the media management logic 340 transmits a new reference voltage value to the memory media 110. The method 500 may then return to block 502, in which the compute device 100 rereads the data from the memory media 110 and attempts error correction until successful. Note, the media management logic 340 may periodically tune the reference voltage value until the voltage is at a suitable level for the present usage on the memory media 110 (e.g., in cases where read operations are relatively high).

Referring back to FIG. 5, once the memory media 110 is at a suitable level (e.g., and there is an ECC adjustment state still present, per block 512), the method 500 proceeds to block 514, in which the compute device 100 resumes, by the media management logic unit 340, the compute operation. Further, in block 516, the compute device 100, by the compute-class ECC logic unit 134, transmits a signal to the state machine 342 indicating that the ECC adjustment state is eliminated (e.g., the memory 104 is in a normal operational state). The method 500 may then proceed to block 518, in which the compute device 100 performs the compute operation on the error corrected read data produced by the successful error correction.

Note, in some cases, multiple retuning attempts of the reference voltage may fail to remedy an ECC adjustment state. In an embodiment, a memory control policy (e.g., maintained in the compute device 100) may specify an amount of attempts to adjust the reference voltage prior to pursuing another action to eliminate the ECC adjustment state. Such a policy may specify other actions to take in place of adjusting the reference voltage (e.g., notifying an administrator, applying redundancy techniques, etc.).

EXAMPLES

Illustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any combination of, the examples described below.

Example 1 includes a memory comprising a memory media; media access circuitry coupled to the memory media, wherein the media access circuitry is to initiate error correction on data read from the memory media; detect an error code adjustment state indicative of a failure in the initiated error correction; adjust a voltage to the memory media to eliminate the error code correction adjustment state; and in response to a determination that the error code correction adjustment state is eliminated, perform the error correction on the read data.

Example 2 includes the subject matter of Example 1, and wherein to initiate the error correction on the data read from the memory media comprises to initiate the error correction on the data read from the memory media as part of a compute operation in the memory.

Example 3 includes the subject matter of any of Examples 1 and 2, and wherein the media access circuitry is further to transmit, by an error correction logic unit in the media access circuitry, a signal to a state machine in the media access circuitry indicative of a presence of the error code correction adjustment state.

Example 4 includes the subject matter of any of Examples 1-3, and wherein to adjust the voltage to the memory media to eliminate the error code correction adjustment state further comprises to pause, by a media management logic in response to the signal, the compute operation.

Example 5 includes the subject matter of any of Examples 1-4, and wherein to adjust the voltage to the memory media to eliminate the error code correction adjustment state further comprises to transmit, by the media management logic, a new reference voltage value to the memory media.

Example 6 includes the subject matter of any of Examples 1-5, and wherein the media access circuitry is further to resume, by the state machine in response to the signal, the compute operation.

Example 7 includes the subject matter of any of Examples 1-6, and wherein the media access circuitry is further to transmit a signal to the state machine indicative of the error code correction adjustment state being eliminated.

Example 8 includes the subject matter of any of Examples 1-7, and wherein the media access circuitry is further to read, from the memory media, the data specified in a request to perform the compute operation.

Example 9 includes the subject matter of any of Examples 1-8, and wherein to read, from the memory media, the data specified in the request to perform the compute operation comprises to read, from the memory media located on a die with the media access circuitry, the data from the memory media.

Example 10 includes the subject matter of any of Examples 1-9, and wherein to read, from the memory media, the data specified in the request to perform the compute operation comprises to read the data specified in the request, the data including error correction code bits.

Example 11 includes a method comprising initiating, by a media access circuitry of a memory, error correction on data read from a memory media coupled with the media access circuitry; detecting an error code adjustment state indicative of a failure in the initiated error correction; adjusting a voltage to the memory media to eliminate the error code correction adjustment state, and in response to determining that the error code correction adjustment state is eliminated, performing the error correction on the read data.

Example 12 includes the subject matter of Example 11, and wherein initiating the error correction on the data read from the memory media comprises initiating the error correction on the data read from the memory media as part of a compute operation in the memory.

Example 13 includes the subject matter of any of Examples 11 and 12, and further including transmitting, by an error correction logic unit in the media access circuitry, a signal to a state machine in the media access circuitry indicative of a presence in the error code correction adjustment state.

Example 14 includes the subject matter of any of Examples 11-13, and wherein adjusting the voltage to the memory media to eliminate the error code correction adjustment state further comprises pausing, by a media management logic in response to the signal, the compute operation.

Example 15 includes the subject matter of any of Examples 11-14, and wherein adjusting the voltage to the memory media to eliminate the error code correction adjustment state further comprises transmitting, by the media management logic, a new reference voltage value to the memory media.

Example 16 includes the subject matter of any of Examples 11-15, and further including resuming, by the state machine in response to the signal, the compute operation.

Example 17 includes the subject matter of any of Examples 11-16, and further including transmitting a signal to the state machine indicative of the error code correction adjustment state being eliminated.

Example 18 includes the subject matter of any of Examples 11-17, and wherein reading, from the memory media, the data specified in the request to perform the compute operation comprises reading, from the memory media located on a die with the media access circuitry, the data from the memory media.

Example 19 includes one or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause media access circuitry included in a memory to initiate error correction on data read from a memory media coupled with the media access circuitry; detect an error code adjustment state indicative of a failure in the initiated error correction; adjust a voltage to the memory media to eliminate the error code correction adjustment state; and in response to a determination that the error code correction adjustment state is eliminated, perform the error correction on the read data.

Example 20 includes the subject matter of Example 19, and wherein to adjust the voltage to the memory media comprises to transmit a new reference voltage value to the memory media. 

1. A memory comprising: a memory media; media access circuitry coupled to the memory media, wherein the media access circuitry is to: initiate error correction on data read from the memory media; detect an error code adjustment state indicative of a failure in the initiated error correction; adjust a voltage to the memory media to eliminate the error code correction adjustment state; and in response to a determination that the error code correction adjustment state is eliminated, perform the error correction on the read data.
 2. The memory of claim 1, wherein to initiate the error correction on the data read from the memory media comprises to initiate the error correction on the data read from the memory media as part of a compute operation in the memory.
 3. The memory of claim 2, wherein the media access circuitry is further to transmit, by an error correction logic unit in the media access circuitry, a signal to a state machine in the media access circuitry indicative of a presence of the error code correction adjustment state.
 4. The memory of claim 3, wherein to adjust the voltage to the memory media to eliminate the error code correction adjustment state further comprises to: pause, by a media management logic in response to the signal, the compute operation.
 5. The memory of claim 4, wherein to adjust the voltage to the memory media to eliminate the error code correction adjustment state further comprises to transmit, by the media management logic, a new reference voltage value to the memory media.
 6. The memory of claim 4, wherein the media access circuitry is further to resume, by the state machine in response to the signal, the compute operation.
 7. The memory of claim 4, wherein the media access circuitry is further to transmit a signal to the state machine indicative of the error code correction adjustment state being eliminated.
 8. The memory of claim 1, wherein the media access circuitry is further to read, from the memory media, the data specified in a request to perform the compute operation.
 9. The memory of claim 8, wherein to read, from the memory media, the data specified in the request to perform the compute operation comprises to read, from the memory media located on a die with the media access circuitry, the data from the memory media.
 10. The memory of claim 8, wherein to read, from the memory media, the data specified in the request to perform the compute operation comprises to read the data specified in the request, the data including error correction code bits.
 11. A method comprising: initiating, by a media access circuitry of a memory, error correction on data read from a memory media coupled with the media access circuitry; detecting an error code adjustment state indicative of a failure in the initiated error correction; adjusting a voltage to the memory media to eliminate the error code correction adjustment state, and in response to determining that the error code correction adjustment state is eliminated, performing the error correction on the read data.
 12. The method of claim 11, wherein initiating the error correction on the data read from the memory media comprises initiating the error correction on the data read from the memory media as part of a compute operation in the memory.
 13. The method of claim 12, further comprising transmitting, by an error correction logic unit in the media access circuitry, a signal to a state machine in the media access circuitry indicative of a presence in the error code correction adjustment state.
 14. The method of claim 13, wherein adjusting the voltage to the memory media to eliminate the error code correction adjustment state further comprises: pausing, by a media management logic in response to the signal, the compute operation.
 15. The method of claim 14, wherein adjusting the voltage to the memory media to eliminate the error code correction adjustment state further comprises transmitting, by the media management logic, a new reference voltage value to the memory media.
 16. The method of claim 14, further comprising resuming, by the state machine in response to the signal, the compute operation.
 17. The method of claim 14, further comprising transmitting a signal to the state machine indicative of the error code correction adjustment state being eliminated.
 18. The method of claim 11, wherein reading, from the memory media, the data specified in the request to perform the compute operation comprises reading, from the memory media located on a die with the media access circuitry, the data from the memory media.
 19. One or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause media access circuitry included in a memory to: initiate error correction on data read from a memory media coupled with the media access circuitry; detect an error code adjustment state indicative of a failure in the initiated error correction; adjust a voltage to the memory media to eliminate the error code correction adjustment state; and in response to a determination that the error code correction adjustment state is eliminated, perform the error correction on the read data.
 20. The one or more machine-readable storage media of claim 19, wherein to adjust the voltage to the memory media comprises to transmit a new reference voltage value to the memory media. 